Description
We would like to support iterative processing by introducing cycles in the graph (known as DAG now, but no longer if we support iterative processing).
Initial idea is as follow:
|----|
v |
A -> B -> C -> D
^ |
|---------|
C has two separate backward streams to A and B. The input ports of A and B that C connects to will have a special attribute on how many window IDs ahead the incoming windows should be treated as, and A and B will be responsible for the initial data for such input ports.
Another idea is to have C advance the window ID on its output ports and have C generate the initial data on its output ports to A and B.
Attachments
Attachments
Issue Links
- is related to
-
APEXCORE-202 Integration with Samoa
-
- Closed
-
- links to
