======================================================================== __STAGE_BEGIN__: stageId=3 stageGroup=HLO stageName=SSA Construction stageTag=ssa ======================================================================== Opt: Running SSA Construction ======================================================================== __IR_DUMP_BEGIN__: stageId=3 stageName=SSA Construction subKind=before Printing IR SSA Construction - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L9 UNWIND I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau I9:call a::_init_(t3) ((t4,t5)) -) GOTO L9 Block L9: Predecessors: L8 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I12:ldvar v1 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L8 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=3 stageName=SSA Construction subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=3 stageName=SSA Construction subKind=after Printing IR SSA Construction - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L9 UNWIND I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau I9:call a::_init_(t3) ((t4,t5)) -) GOTO L9 Block L9: Predecessors: L8 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L8 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=3 stageName=SSA Construction subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=3 stageGroup=HLO stageName=SSA Construction stageTag=ssa ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=4 stageGroup=HLO stageName=Guarded Devirtualization of Virtual Calls stageTag=devirt ======================================================================== Opt: Running Guarded Devirtualization of Virtual Calls ======================================================================== __IR_DUMP_BEGIN__: stageId=4 stageName=Guarded Devirtualization of Virtual Calls subKind=before Printing IR Guarded Devirtualization of Virtual Calls - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L9 UNWIND I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau I9:call a::_init_(t3) ((t4,t5)) -) GOTO L9 Block L9: Predecessors: L8 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L8 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=4 stageName=Guarded Devirtualization of Virtual Calls subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=4 stageName=Guarded Devirtualization of Virtual Calls subKind=after Printing IR Guarded Devirtualization of Virtual Calls - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L9 UNWIND I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau I9:call a::_init_(t3) ((t4,t5)) -) GOTO L9 Block L9: Predecessors: L8 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L8 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=4 stageName=Guarded Devirtualization of Virtual Calls subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=4 stageGroup=HLO stageName=Guarded Devirtualization of Virtual Calls stageTag=devirt ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=5 stageGroup=HLO stageName=Method Inlining stageTag=inline ======================================================================== Opt: Running Method Inlining ======================================================================== __IR_DUMP_BEGIN__: stageId=5 stageName=Method Inlining subKind=before Printing IR Method Inlining - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L9 UNWIND I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau I9:call a::_init_(t3) ((t4,t5)) -) GOTO L9 Block L9: Predecessors: L8 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L8 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=5 stageName=Method Inlining subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=5 stageName=Method Inlining subKind=after Printing IR Method Inlining - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I47:copy t3 -) t17:cls:a I35:tauisnonnull t17 -) t18:tau I36:tauhastype t17,cls:a -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I59:copy t17 -) t21:cls:java/lang/Object I50:tauisnonnull t21 -) t22:tau I51:tauhastype t21,cls:java/lang/Object -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L17 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L17 Block L17: Predecessors: L20 Successors: L14 I44:L17: GOTO L14 Block L14: Predecessors: L17 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 D15 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=5 stageName=Method Inlining subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=5 stageGroup=HLO stageName=Method Inlining stageTag=inline ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=10 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== Opt: Running Unreachable Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=10 stageName=Unreachable Code Elimination subKind=before Printing IR Unreachable Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I47:copy t3 -) t17:cls:a I35:tauisnonnull t17 -) t18:tau I36:tauhastype t17,cls:a -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I59:copy t17 -) t21:cls:java/lang/Object I50:tauisnonnull t21 -) t22:tau I51:tauhastype t21,cls:java/lang/Object -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L17 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L17 Block L17: Predecessors: L20 Successors: L14 I44:L17: GOTO L14 Block L14: Predecessors: L17 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 D15 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=10 stageName=Unreachable Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=10 stageName=Unreachable Code Elimination subKind=after Printing IR Unreachable Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I47:copy t3 -) t17:cls:a I35:tauisnonnull t17 -) t18:tau I36:tauhastype t17,cls:a -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I59:copy t17 -) t21:cls:java/lang/Object I50:tauisnonnull t21 -) t22:tau I51:tauhastype t21,cls:java/lang/Object -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L17 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L17 Block L17: Predecessors: L20 Successors: L14 I44:L17: GOTO L14 Block L14: Predecessors: L17 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=10 stageName=Unreachable Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=10 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=12 stageGroup=HLO stageName=Perform simplification pass stageTag=simplify ======================================================================== Opt: Running Perform simplification pass ======================================================================== __IR_DUMP_BEGIN__: stageId=12 stageName=Perform simplification pass subKind=before Printing IR Perform simplification pass - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I47:copy t3 -) t17:cls:a I35:tauisnonnull t17 -) t18:tau I36:tauhastype t17,cls:a -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I59:copy t17 -) t21:cls:java/lang/Object I50:tauisnonnull t21 -) t22:tau I51:tauhastype t21,cls:java/lang/Object -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L14 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L14 Block L14: Predecessors: L20 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I16:tauhastype t3,cls:a -) t10:tau I17:call a::work(t3) ((t9,t10)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=12 stageName=Perform simplification pass subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=12 stageName=Perform simplification pass subKind=after Printing IR Perform simplification pass - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I60:copy t3 -) t17:cls:a I62:copy t24 -) t18:tau I63:copy t24 -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I64:copy t3 -) t21:cls:java/lang/Object I65:copy t24 -) t22:tau I66:copy t24 -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L14 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L14 Block L14: Predecessors: L20 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I67:copy t24 -) t10:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=12 stageName=Perform simplification pass subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=12 stageGroup=HLO stageName=Perform simplification pass stageTag=simplify ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=13 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== Opt: Running Dead Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=13 stageName=Dead Code Elimination subKind=before Printing IR Dead Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I5:tauhastype t1,cls:java/lang/String[] -) t2:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L12 I28:L8: I7:tausafe() -) t4:tau I8:tauunsafe() -) t5:tau GOTO L12 Block L12: Predecessors: L8 Successors: L18 I33:--- MethodEntry(a::_init_): () I45:--- MethodEntry(a::_init_): () I60:copy t3 -) t17:cls:a I62:copy t24 -) t18:tau I63:copy t24 -) t19:tau I37:tauunsafe() -) t20:tau GOTO L18 Block L18: Predecessors: L12 Successors: L20 I48:--- MethodEntry(java/lang/Object::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I64:copy t3 -) t21:cls:java/lang/Object I65:copy t24 -) t22:tau I66:copy t24 -) t23:tau GOTO L20 Block L20: Predecessors: L18 Successors: L14 I54:L20: I58:+++ MethodEnd(java/lang/Object::_init_) () GOTO L14 Block L14: Predecessors: L20 Successors: L9 I41:L14: I46:+++ MethodEnd(a::_init_) () GOTO L9 Block L9: Predecessors: L14 Successors: L1 I29:L9: I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L9 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I67:copy t24 -) t10:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=13 stageName=Dead Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=13 stageName=Dead Code Elimination subKind=after Printing IR Dead Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=13 stageName=Dead Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=13 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=14 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== Opt: Running Unreachable Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=14 stageName=Unreachable Code Elimination subKind=before Printing IR Unreachable Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=14 stageName=Unreachable Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=14 stageName=Unreachable Code Elimination subKind=after Printing IR Unreachable Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=14 stageName=Unreachable Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=14 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=15 stageGroup=HLO stageName=Lazy Exception Throwing Optimization stageTag=lazyexc ======================================================================== Opt: Running Lazy Exception Throwing Optimization ======================================================================== __IR_DUMP_BEGIN__: stageId=15 stageName=Lazy Exception Throwing Optimization subKind=before Printing IR Lazy Exception Throwing Optimization - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=15 stageName=Lazy Exception Throwing Optimization subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=15 stageName=Lazy Exception Throwing Optimization subKind=after Printing IR Lazy Exception Throwing Optimization - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=15 stageName=Lazy Exception Throwing Optimization subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=15 stageGroup=HLO stageName=Lazy Exception Throwing Optimization stageTag=lazyexc ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=16 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== Opt: Running Dead Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=16 stageName=Dead Code Elimination subKind=before Printing IR Dead Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=16 stageName=Dead Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=16 stageName=Dead Code Elimination subKind=after Printing IR Dead Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=16 stageName=Dead Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=16 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=17 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== Opt: Running Unreachable Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=17 stageName=Unreachable Code Elimination subKind=before Printing IR Unreachable Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=17 stageName=Unreachable Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=17 stageName=Unreachable Code Elimination subKind=after Printing IR Unreachable Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=17 stageName=Unreachable Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=17 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=18 stageGroup=HLO stageName=Redundant Ld-St Elimination stageTag=memopt ======================================================================== Opt: Running Redundant Ld-St Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=18 stageName=Redundant Ld-St Elimination subKind=before Printing IR Redundant Ld-St Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I15:tausafe() -) t9:tau I17:call a::work(t3) ((t9,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=18 stageName=Redundant Ld-St Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=18 stageName=Redundant Ld-St Elimination subKind=after Printing IR Redundant Ld-St Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I69:tauunsafe() -) t26:tau I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I68:tauedge() -) t25:tau I70:copy t24 -) t9:tau I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I71:tauedge() -) t27:tau I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=18 stageName=Redundant Ld-St Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=18 stageGroup=HLO stageName=Redundant Ld-St Elimination stageTag=memopt ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=19 stageGroup=HLO stageName=Perform simplification pass stageTag=simplify ======================================================================== Opt: Running Perform simplification pass ======================================================================== __IR_DUMP_BEGIN__: stageId=19 stageName=Perform simplification pass subKind=before Printing IR Perform simplification pass - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I69:tauunsafe() -) t26:tau I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I68:tauedge() -) t25:tau I70:copy t24 -) t9:tau I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I71:tauedge() -) t27:tau I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=19 stageName=Perform simplification pass subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=19 stageName=Perform simplification pass subKind=after Printing IR Perform simplification pass - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I69:tauunsafe() -) t26:tau I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I68:tauedge() -) t25:tau I72:copy t24 -) t9:tau I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I71:tauedge() -) t27:tau I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=19 stageName=Perform simplification pass subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=19 stageGroup=HLO stageName=Perform simplification pass stageTag=simplify ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=20 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== Opt: Running Dead Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=20 stageName=Dead Code Elimination subKind=before Printing IR Dead Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I69:tauunsafe() -) t26:tau I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I68:tauedge() -) t25:tau I72:copy t24 -) t9:tau I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I71:tauedge() -) t27:tau I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=20 stageName=Dead Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=20 stageName=Dead Code Elimination subKind=after Printing IR Dead Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=20 stageName=Dead Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=20 stageGroup=HLO stageName=Dead Code Elimination stageTag=dce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=21 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== Opt: Running Unreachable Code Elimination ======================================================================== __IR_DUMP_BEGIN__: stageId=21 stageName=Unreachable Code Elimination subKind=before Printing IR Unreachable Code Elimination - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=21 stageName=Unreachable Code Elimination subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=21 stageName=Unreachable Code Elimination subKind=after Printing IR Unreachable Code Elimination - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=21 stageName=Unreachable Code Elimination subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=21 stageGroup=HLO stageName=Unreachable Code Elimination stageTag=uce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=22 stageGroup=HLO stageName=Code Lowering / Fast Path Inlining stageTag=lower ======================================================================== Opt: Running Code Lowering / Fast Path Inlining ======================================================================== __IR_DUMP_BEGIN__: stageId=22 stageName=Code Lowering / Fast Path Inlining subKind=before Printing IR Code Lowering / Fast Path Inlining - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) t24:tau I6:newobj cls:a -) t3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(t3) ((t24,t24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=22 stageName=Code Lowering / Fast Path Inlining subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=22 stageName=Code Lowering / Fast Path Inlining subKind=after Printing IR Code Lowering / Fast Path Inlining - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=22 stageName=Code Lowering / Fast Path Inlining subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=22 stageGroup=HLO stageName=Code Lowering / Fast Path Inlining stageTag=lower ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=23 stageGroup=HLO stageName=SSA Deconstruction stageTag=dessa ======================================================================== Opt: Running SSA Deconstruction ======================================================================== __IR_DUMP_BEGIN__: stageId=23 stageName=SSA Deconstruction subKind=before Printing IR SSA Deconstruction - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1.14:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I32:phi(v1.14, v1.16) -) v1.15:int32 I12:ldvar v1.15 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1.16:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=23 stageName=SSA Deconstruction subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=23 stageName=SSA Deconstruction subKind=after Printing IR SSA Deconstruction - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I12:ldvar v1 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=23 stageName=SSA Deconstruction subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=23 stageGroup=HLO stageName=SSA Deconstruction stageTag=dessa ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=24 stageGroup=HLO stageName=Perform edge annotation pass based on static heuristics stageTag=statprof ======================================================================== Opt: Running Perform edge annotation pass based on static heuristics ======================================================================== __IR_DUMP_BEGIN__: stageId=24 stageName=Perform edge annotation pass based on static heuristics subKind=before Printing IR Perform edge annotation pass based on static heuristics - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I12:ldvar v1 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=24 stageName=Perform edge annotation pass based on static heuristics subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=24 stageName=Perform edge annotation pass based on static heuristics subKind=after Printing IR Perform edge annotation pass based on static heuristics - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I12:ldvar v1 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=24 stageName=Perform edge annotation pass based on static heuristics subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=24 stageGroup=HLO stageName=Perform edge annotation pass based on static heuristics stageTag=statprof ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=25 stageGroup=HLO stageName=Basic Block based Global Operand Analysis stageTag=markglobals ======================================================================== Opt: Running Basic Block based Global Operand Analysis ======================================================================== __IR_DUMP_BEGIN__: stageId=25 stageName=Basic Block based Global Operand Analysis subKind=before Printing IR Basic Block based Global Operand Analysis - before ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I12:ldvar v1 -) g7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 g7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add g7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=25 stageName=Basic Block based Global Operand Analysis subKind=before ======================================================================== ======================================================================== __IR_DUMP_BEGIN__: stageId=25 stageName=Basic Block based Global Operand Analysis subKind=after Printing IR Basic Block based Global Operand Analysis - after ======================================================================== -------- irDump: a::main -------- Block ENTRY_L0: Predecessors: Successors: L8 UNWIND I0:--- MethodEntry(a::main): () I4:defarg -) t1:cls:java/lang/String[] I61:tausafe() -) g24:tau I6:newobj cls:a -) g3:cls:a GOTO L8 Block L8: Predecessors: ENTRY_L0 Successors: L1 I28:L8: I45:--- MethodEntry(a::_init_): () I57:--- MethodEntry(java/lang/Object::_init_): () I58:+++ MethodEnd(java/lang/Object::_init_) () I46:+++ MethodEnd(a::_init_) () I10:ldci4 #0 -) t6:int32 I11:stvar t6 -) v1:int32 GOTO L1 Block L1: Predecessors: L10 L8 Successors: L3 L2 I1:L1: I12:ldvar v1 -) t7:int32 I13:ldci4 #20000 -) t8:int32 I14:if cge.i4 t7, t8 goto L3 GOTO L2 Block L2: Predecessors: L1 Successors: L10 UNWIND I2:L2: I17:call a::work(g3) ((g24,g24)) -) t11:cls:man GOTO L10 Block UNWIND: Predecessors: ENTRY_L0 L2 Successors: EXIT I26:L6: GOTO EXIT Block L10: Predecessors: L2 Successors: L1 I30:L10: I18:ldci4 #1 -) t12:int32 I19:add t7, t12 -) t13:int32 I20:stvar t13 -) v1:int32 GOTO L1 Block L3: Predecessors: L1 Successors: RETURN I3:L3: I23:return Block RETURN: Predecessors: L3 Successors: EXIT I25:L5: GOTO EXIT Block EXIT: Predecessors: RETURN UNWIND Successors: I27:L7: ======================================================================== __IR_DUMP_END__: stageId=25 stageName=Basic Block based Global Operand Analysis subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=25 stageGroup=HLO stageName=Basic Block based Global Operand Analysis stageTag=markglobals ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=26 stageGroup=IA32 stageName=hir2lir stageTag=hir2lir ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=26 stageName=hir2lir subKind=after.opnds Printing IR hir2lir - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after hir2lir .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm ======================================================================== __IR_DUMP_END__: stageId=26 stageName=hir2lir subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=26 stageName=hir2lir subKind=after Printing IR hir2lir - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after hir2lir ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_2 BB_6 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 Successors: EN_9 [Prob=1] BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_3 [Prob=1](backedge) I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=26 stageName=hir2lir subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=26 stageGroup=IA32 stageName=hir2lir stageTag=hir2lir ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=28 stageGroup=IA32 stageName=bbp stageTag=bbp ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=28 stageName=bbp subKind=after.opnds Printing IR bbp - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after bbp .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm o18:ptr:intptr addr=o18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null o19(20):int32 addr=o19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o20(FS:[o19(20)]):ptr:int8 addr=o20(FS:[o19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem o21(4):ptr:intptr addr=o21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o22(0):int32 addr=o22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o23[o18+o22(0)]:int32 addr=o23[o18+o22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem o24(0):int32 addr=o24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o25(0):int32 addr=o25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o26(0:h:EnableThreadSuspension):int32 addr=o26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=28 stageName=bbp subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=28 stageName=bbp subKind=after.liveness Printing IR bbp - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after bbp ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) o18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_10 BB_12 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) o18(18) Live at exit: t4(4) t9(9) o18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) o18(18) Live at exit: t4(4) t9(9) o18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) o18(18) Live at exit: v0(0) t4(4) o18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_12 [Prob=1](Br=I16) Live at entry: v0(0) t4(4) o18(18) Live at exit: v0(0) t4(4) o18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_12 [Prob=1] DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) o18(18) Live at exit: v0(0) t4(4) o18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_12 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 BB_14 Successors: BB_3 [Prob=1](backedge) Live at entry: v0(0) t4(4) o18(18) Live at exit: v0(0) t4(4) o18(18) BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=28 stageName=bbp subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=28 stageName=bbp subKind=after Printing IR bbp - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after bbp ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: o18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD o20(FS:[o19(20)]):ptr:int8,o21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_10 BB_12 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_12 [Prob=1](Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP o23[o18+o22(0)]:int32,o24(0):int32 I16: JNZ BB_14 o25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_12 [Prob=1] DN_13 [Prob=0](loopexit) I17: CALL o26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_12 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 BB_14 Successors: BB_3 [Prob=1](backedge) BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=28 stageName=bbp subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=28 stageGroup=IA32 stageName=bbp stageTag=bbp ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=29 stageGroup=IA32 stageName=btr stageTag=btr ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=29 stageName=btr subKind=after.opnds Printing IR btr - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after btr .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=29 stageName=btr subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=29 stageName=btr subKind=after.liveness Printing IR btr - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after btr ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=29 stageName=btr subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=29 stageName=btr subKind=after Printing IR btr - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after btr ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=29 stageName=btr subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=29 stageGroup=IA32 stageName=btr stageTag=btr ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=30 stageGroup=IA32 stageName=gcpoints stageTag=gcpoints ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=30 stageName=gcpoints subKind=after.opnds Printing IR gcpoints - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after gcpoints .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=30 stageName=gcpoints subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=30 stageName=gcpoints subKind=after.liveness Printing IR gcpoints - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after gcpoints ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=30 stageName=gcpoints subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=30 stageName=gcpoints subKind=after Printing IR gcpoints - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after gcpoints ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=30 stageName=gcpoints subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=30 stageGroup=IA32 stageName=gcpoints stageTag=gcpoints ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=31 stageGroup=IA32 stageName=cafl stageTag=cafl ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=31 stageName=cafl subKind=after.opnds Printing IR cafl - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after cafl .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=31 stageName=cafl subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=31 stageName=cafl subKind=after.liveness Printing IR cafl - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after cafl ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=31 stageName=cafl subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=31 stageName=cafl subKind=after Printing IR cafl - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after cafl ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=31 stageName=cafl subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=31 stageGroup=IA32 stageName=cafl stageTag=cafl ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=32 stageGroup=IA32 stageName=cg_dce stageTag=cg_dce ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=32 stageName=cg_dce subKind=after.opnds Printing IR cg_dce - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after cg_dce .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=32 stageName=cg_dce subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=32 stageName=cg_dce subKind=after.liveness Printing IR cg_dce - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after cg_dce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=32 stageName=cg_dce subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=32 stageName=cg_dce subKind=after Printing IR cg_dce - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after cg_dce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=32 stageName=cg_dce subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=32 stageGroup=IA32 stageName=cg_dce stageTag=cg_dce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=33 stageGroup=IA32 stageName=i8l stageTag=i8l ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=33 stageName=i8l subKind=after.opnds Printing IR i8l - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after i8l .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=33 stageName=i8l subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=33 stageName=i8l subKind=after.liveness Printing IR i8l - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after i8l ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=33 stageName=i8l subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=33 stageName=i8l subKind=after Printing IR i8l - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after i8l ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=33 stageName=i8l subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=33 stageGroup=IA32 stageName=i8l stageTag=i8l ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=34 stageGroup=IA32 stageName=api_magic stageTag=api_magic ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=34 stageName=api_magic subKind=after.opnds Printing IR api_magic - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after api_magic .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=34 stageName=api_magic subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=34 stageName=api_magic subKind=after.liveness Printing IR api_magic - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after api_magic ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(4) t9(9) t18(18) Live at exit: t4(4) t9(9) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: t4(4) t9(9) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=34 stageName=api_magic subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=34 stageName=api_magic subKind=after Printing IR api_magic - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after api_magic ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I7: (AD:t9:int32) =CopyPseudoInst/MOV (AU:v0:int32) I8: (ID:v11(EFLGS):uint32) =CMP t9:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD t9:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=34 stageName=api_magic subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=34 stageGroup=IA32 stageName=api_magic stageTag=api_magic ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=35 stageGroup=IA32 stageName=early_prop stageTag=early_prop ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=35 stageName=early_prop subKind=after.opnds Printing IR early_prop - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after early_prop .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=35 stageName=early_prop subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=35 stageName=early_prop subKind=after.liveness Printing IR early_prop - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after early_prop ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=35 stageName=early_prop subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=35 stageName=early_prop subKind=after Printing IR early_prop - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after early_prop ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD v0:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=35 stageName=early_prop subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=35 stageGroup=IA32 stageName=early_prop stageTag=early_prop ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=36 stageGroup=IA32 stageName=peephole stageTag=peephole ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=36 stageName=peephole subKind=after.opnds Printing IR peephole - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after peephole .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=36 stageName=peephole subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=36 stageName=peephole subKind=after.liveness Printing IR peephole - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after peephole ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=36 stageName=peephole subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=36 stageName=peephole subKind=after Printing IR peephole - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after peephole ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I14: t18:ptr:intptr (ID:v11(EFLGS):uint32) =ADD t20(FS:[t19(20)]):ptr:int8,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I11: t16:int32 (ID:v11(EFLGS):uint32) =ADD v0:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=36 stageName=peephole subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=36 stageGroup=IA32 stageName=peephole stageTag=peephole ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=37 stageGroup=IA32 stageName=native stageTag=native ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=37 stageName=native subKind=after.opnds Printing IR native - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after native .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(0):int16 addr=t17(0):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=37 stageName=native subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=37 stageName=native subKind=after.liveness Printing IR native - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after native ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=37 stageName=native subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=37 stageName=native subKind=after Printing IR native - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after native ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t4:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I19: (AD:t18:ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD t18:ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I18: (AD:t16:int32) =CopyPseudoInst/MOV (AU:v0:int32) I11: (ID:v11(EFLGS):uint32) =ADD t16:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(0):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=37 stageName=native subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=37 stageGroup=IA32 stageName=native stageTag=native ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=38 stageGroup=IA32 stageName=constraints stageTag=constraints ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=38 stageName=constraints subKind=after.opnds Printing IR constraints - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after constraints .................................................................... v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Null t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Null t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t6(0):int32 addr=t6(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t7(0):int32 addr=t7(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t9:int32 addr=t9:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t16:int32 addr=t16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm Location constraint: Sz16:Imm t18:ptr:intptr addr=t18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EBX|EBP|ESI|EDI} Location constraint: Null t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t23[t18+t22(0)]:int32 addr=t23[t18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm o27:cls:a addr=o27:cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Null ======================================================================== __IR_DUMP_END__: stageId=38 stageName=constraints subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=38 stageName=constraints subKind=after.liveness Printing IR constraints - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after constraints ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(4) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] Live at entry: t4(4) Live at exit: v0(0) t4(4) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] Live at entry: v0(0) t4(4) Live at exit: v0(0) t4(4) t18(18) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) Live at entry: v0(0) t4(4) t18(18) Live at exit: v0(0) t4(4) t18(18) DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] Live at entry: Live at exit: UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=38 stageName=constraints subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=38 stageName=constraints subKind=after Printing IR constraints - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after constraints ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:o27:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I20: (AD:t4:cls:a) =CopyPseudoInst/MOV (AU:o27:cls:a) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_10 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) BB_10 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_2 Successors: BB_3 [Prob=1] I19: (AD:t18:ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD t18:ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_11 BB_14 BB_10 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_11 [Prob=1] I18: (AD:t16:int32) =CopyPseudoInst/MOV (AU:v0:int32) I11: (ID:v11(EFLGS):uint32) =ADD t16:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t16:int32) BB_11 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I15: (ID:v11(EFLGS):uint32) =CMP t23[t18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_11 Successors: BB_3 [Prob=1](backedge) DN_13 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 DN_13 PersistentId = 0 ExecCnt = 0 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 Successors: UN_5 [Prob=1] UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 BB_4 DN_13 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=38 stageName=constraints subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=38 stageGroup=IA32 stageName=constraints stageTag=constraints ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=39 stageGroup=IA32 stageName=cg_dce stageTag=cg_dce ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=39 stageName=cg_dce subKind=after.opnds Printing IR cg_dce - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after cg_dce .................................................................... t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Null t27:cls:a addr=t27:cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Null t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t4:cls:a addr=t4:cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Null v0:int32 addr=v0:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Null t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s18:ptr:intptr addr=s18:ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EBX|EBP|ESI|EDI} Location constraint: Null t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t14:cls:man addr=t14:cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX} Location constraint: Null t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s16:int32 addr=s16:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t23[s18+t22(0)]:int32 addr=t23[s18+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm Location constraint: Sz16:Imm ======================================================================== __IR_DUMP_END__: stageId=39 stageName=cg_dce subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=39 stageName=cg_dce subKind=after.liveness Printing IR cg_dce - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after cg_dce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(5) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Live at entry: t4(5) Live at exit: t4(5) v0(6) s18(8) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=0](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=39 stageName=cg_dce subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=39 stageName=cg_dce subKind=after Printing IR cg_dce - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after cg_dce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t27:cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I20: (AD:t4:cls:a) =CopyPseudoInst/MOV (AU:t27:cls:a) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0:int32) =CopyPseudoInst/MOV (AU:t8(0):int32) I19: (AD:s18:ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD s18:ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0:int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14:cls:man) =CALL t13(0:m:a.work):int32 (AU:t4:cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=0](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I18: (AD:s16:int32) =CopyPseudoInst/MOV (AU:v0:int32) I11: (ID:v11(EFLGS):uint32) =ADD s16:int32,t15(1):int32 I12: (AD:v0:int32) =CopyPseudoInst/MOV (AU:s16:int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=0](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=39 stageName=cg_dce subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=39 stageGroup=IA32 stageName=cg_dce stageTag=cg_dce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=40 stageGroup=IA32 stageName=bp_regalloc stageTag=bp_regalloc ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=40 stageName=bp_regalloc subKind=after.opnds Printing IR bp_regalloc - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after bp_regalloc .................................................................... t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Null t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm Location constraint: Sz16:Imm ======================================================================== __IR_DUMP_END__: stageId=40 stageName=bp_regalloc subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=40 stageName=bp_regalloc subKind=after.liveness Printing IR bp_regalloc - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after bp_regalloc ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(5) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Live at entry: t4(5) Live at exit: t4(5) v0(6) s18(8) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=40 stageName=bp_regalloc subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=40 stageName=bp_regalloc subKind=after Printing IR bp_regalloc - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after bp_regalloc ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I20: (AD:t4(ESI):cls:a) =CopyPseudoInst/MOV (AU:t27(EAX):cls:a) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:t8(0):int32) I19: (AD:s18(EBP):ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=40 stageName=bp_regalloc subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=40 stageGroup=IA32 stageName=bp_regalloc stageTag=bp_regalloc ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=41 stageGroup=IA32 stageName=bp_regalloc stageTag=bp_regalloc ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=41 stageName=bp_regalloc subKind=after.opnds Printing IR bp_regalloc - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after bp_regalloc .................................................................... t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Null t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Mem Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm Location constraint: Sz16:Imm ======================================================================== __IR_DUMP_END__: stageId=41 stageName=bp_regalloc subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=41 stageName=bp_regalloc subKind=after.liveness Printing IR bp_regalloc - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after bp_regalloc ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(5) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Live at entry: t4(5) Live at exit: t4(5) v0(6) s18(8) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=41 stageName=bp_regalloc subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=41 stageName=bp_regalloc subKind=after Printing IR bp_regalloc - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after bp_regalloc ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t1:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I20: (AD:t4(ESI):cls:a) =CopyPseudoInst/MOV (AU:t27(EAX):cls:a) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:t8(0):int32) I19: (AD:s18(EBP):ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=41 stageName=bp_regalloc subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=41 stageGroup=IA32 stageName=bp_regalloc stageTag=bp_regalloc ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=42 stageGroup=IA32 stageName=spillgen stageTag=spillgen ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=42 stageName=spillgen subKind=after.opnds Printing IR spillgen - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after spillgen .................................................................... t1:cls:java/lang/String[] addr=t1:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Null t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm o28(ESP):uint32 addr=o28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} o29(0):int32 addr=o29(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o30[o28(ESP)+o29(0)]:cls:java/lang/String[] addr=o30[o28(ESP)+o29(0)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem ======================================================================== __IR_DUMP_END__: stageId=42 stageName=spillgen subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=42 stageName=spillgen subKind=after.liveness Printing IR spillgen - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after spillgen ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: o28(25) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(5) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Live at entry: t4(5) Live at exit: t4(5) v0(6) s18(8) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) Live at entry: t4(5) v0(6) s18(8) Live at exit: t4(5) v0(6) s18(8) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=42 stageName=spillgen subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=42 stageName=spillgen subKind=after Printing IR spillgen - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after spillgen ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:o30[o28(ESP)+o29(0)]:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I20: (AD:t4(ESI):cls:a) =CopyPseudoInst/MOV (AU:t27(EAX):cls:a) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I6: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:t8(0):int32) I19: (AD:s18(EBP):ptr:intptr) =CopyPseudoInst/MOV (AU:t20(FS:[t19(20)]):ptr:int8) I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=42 stageName=spillgen subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=42 stageGroup=IA32 stageName=spillgen stageTag=spillgen ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=43 stageGroup=IA32 stageName=copy stageTag=copy ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=43 stageName=copy subKind=after.opnds Printing IR copy - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after copy .................................................................... t30[t28(ESP)+t29(0)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(0)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(0):int32 addr=t29(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm ======================================================================== __IR_DUMP_END__: stageId=43 stageName=copy subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=43 stageName=copy subKind=after.liveness Printing IR copy - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after copy ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Live at entry: t28(1) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=43 stageName=copy subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=43 stageName=copy subKind=after Printing IR copy - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after copy ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] I0: (AD:t30[t28(ESP)+t29(0)]:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] I29: PUSH t3(0:ah:cls:a):ptr:intptr I28: PUSH t2(0:sz:cls:a):int32 I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I26: (ID:v11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_14 BB_2 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) I24: PUSH t4(ESI):cls:a I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JNZ BB_14 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: BB_3 [Prob=1](backedge) UN_5 [Prob=1e-007](loopexit) I17: CALL t26(0:h:EnableThreadSuspension):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=43 stageName=copy subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=43 stageGroup=IA32 stageName=copy stageTag=copy ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=44 stageGroup=IA32 stageName=i586 stageTag=i586 ======================================================================== ======================================================================== __STAGE_END__: stageId=44 stageGroup=IA32 stageName=i586 stageTag=i586 ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=45 stageGroup=IA32 stageName=layout stageTag=layout ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=45 stageName=layout subKind=after.opnds Printing IR layout - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after layout .................................................................... t30[t28(ESP)+t29(0)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(0)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(0):int32 addr=t29(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm o31(0):int32 addr=o31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=45 stageName=layout subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=45 stageName=layout subKind=after.liveness Printing IR layout - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after layout ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Live at entry: t28(1) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=45 stageName=layout subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=45 stageName=layout subKind=after Printing IR layout - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after layout ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 I0: (AD:t30[t28(ESP)+t29(0)]:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 I29: PUSH t3(0:ah:cls:a):ptr:intptr I28: PUSH t2(0:sz:cls:a):int32 I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I26: (ID:v11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 I24: PUSH t4(ESI):cls:a I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JZ BB_3 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 I17: CALL t26(0:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog I30: JMP o31(0):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=45 stageName=layout subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=45 stageGroup=IA32 stageName=layout stageTag=layout ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=46 stageGroup=IA32 stageName=rce stageTag=rce ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=46 stageName=rce subKind=after.opnds Printing IR rce - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after rce .................................................................... t30[t28(ESP)+t29(0)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(0)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(0):int32 addr=t29(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm v11(EFLGS):uint32 addr=v11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm o31(0):int32 addr=o31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm ======================================================================== __IR_DUMP_END__: stageId=46 stageName=rce subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=46 stageName=rce subKind=after.liveness Printing IR rce - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after rce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Live at entry: t28(1) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=46 stageName=rce subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=46 stageName=rce subKind=after Printing IR rce - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after rce ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 I0: (AD:t30[t28(ESP)+t29(0)]:cls:java/lang/String[]) =EntryPointPseudoInst BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 I29: PUSH t3(0:ah:cls:a):ptr:intptr I28: PUSH t2(0:sz:cls:a):int32 I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I26: (ID:v11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 I14: (ID:v11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 I8: (ID:v11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:v11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 I24: PUSH t4(ESI):cls:a I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:v11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:v11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JZ BB_3 t25(0):int32 (IU:v11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 I17: CALL t26(0:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog I30: JMP o31(0):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=46 stageName=rce subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=46 stageGroup=IA32 stageName=rce stageTag=rce ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=47 stageGroup=IA32 stageName=stack stageTag=stack ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=47 stageName=stack subKind=after.opnds Printing IR stack - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after stack .................................................................... t30[t28(ESP)+t29(4)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(4)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(4):int32 addr=t29(4):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s11(EFLGS):uint32 addr=s11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t31(0):int32 addr=t31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm o32(ESI):uint32 addr=o32(ESI):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} o33(EBP):uint32 addr=o33(EBP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} o34(EBX):uint32 addr=o34(EBX):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} ======================================================================== __IR_DUMP_END__: stageId=47 stageName=stack subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=47 stageName=stack subKind=after.liveness Printing IR stack - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after stack ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Live at entry: t28(1) o32(28) o33(29) o34(30) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=47 stageName=stack subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=47 stageName=stack subKind=after Printing IR stack - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after stack ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 I0: (AD:t30[t28(ESP)+t29(4)]:cls:java/lang/String[]) =EntryPointPseudoInst I33: PUSH o34(EBX):uint32 I32: PUSH o33(EBP):uint32 I31: PUSH o32(ESI):uint32 BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 I29: PUSH t3(0:ah:cls:a):ptr:intptr I28: PUSH t2(0:sz:cls:a):int32 I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I26: (ID:s11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 I14: (ID:s11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 I8: (ID:s11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:s11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 I24: PUSH t4(ESI):cls:a I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:s11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:s11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JZ BB_3 t25(0):int32 (IU:s11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 I17: CALL t26(0:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog I30: JMP t31(0):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL I34: POP o32(ESI):uint32 I35: POP o33(EBP):uint32 I36: POP o34(EBX):uint32 I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=47 stageName=stack subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=47 stageGroup=IA32 stageName=stack stageTag=stack ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=48 stageGroup=IA32 stageName=peephole stageTag=peephole ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=48 stageName=peephole subKind=after.opnds Printing IR peephole - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after peephole .................................................................... t30[t28(ESP)+t29(4)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(4)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(4):int32 addr=t29(4):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(0:h:NewObj_UsingVtable):int32 addr=t5(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(0:sz:cls:a):int32 addr=t2(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(0:ah:cls:a):ptr:intptr addr=t3(0):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s11(EFLGS):uint32 addr=s11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(0:m:a.work):int32 addr=t13(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(0:h:EnableThreadSuspension):int32 addr=t26(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t31(0):int32 addr=t31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t32(ESI):uint32 addr=t32(ESI):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} t33(EBP):uint32 addr=t33(EBP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t34(EBX):uint32 addr=t34(EBX):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} ======================================================================== __IR_DUMP_END__: stageId=48 stageName=peephole subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=48 stageName=peephole subKind=after.liveness Printing IR peephole - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after peephole ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Live at entry: t28(1) t32(28) t33(29) t34(30) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=48 stageName=peephole subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=48 stageName=peephole subKind=after Printing IR peephole - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after peephole ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 I0: (AD:t30[t28(ESP)+t29(4)]:cls:java/lang/String[]) =EntryPointPseudoInst I33: PUSH t34(EBX):uint32 I32: PUSH t33(EBP):uint32 I31: PUSH t32(ESI):uint32 BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 I29: PUSH t3(0:ah:cls:a):ptr:intptr I28: PUSH t2(0:sz:cls:a):int32 I1: (AD:t27(EAX):cls:a) =CALL t5(0:h:NewObj_UsingVtable):int32 (AU:t2(0:sz:cls:a):int32,t3(0:ah:cls:a):ptr:intptr) I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 I2: MethodEntryPseudoInst[a.]--- I3: MethodEntryPseudoInst[java/lang/Object.]--- I4: MethodEndPseudoInst[java/lang/Object.]+++ I5: MethodEndPseudoInst[a.]+++ I26: (ID:s11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 I14: (ID:s11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 I8: (ID:s11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 I9: JNL BB_7_epilog t12(0):int32 (IU:s11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 I24: PUSH t4(ESI):cls:a I10: (AD:t14(EAX):cls:man) =CALL t13(0:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) I11: (ID:s11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) I15: (ID:s11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 I16: JZ BB_3 t25(0):int32 (IU:s11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 I17: CALL t26(0:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog I30: JMP t31(0):int32 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL I34: POP t32(ESI):uint32 I35: POP t33(EBP):uint32 I36: POP t34(EBX):uint32 I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=48 stageName=peephole subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=48 stageGroup=IA32 stageName=peephole stageTag=peephole ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=49 stageGroup=IA32 stageName=emitter stageTag=emitter ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=49 stageName=emitter subKind=after.opnds Printing IR emitter - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after emitter .................................................................... t30[t28(ESP)+t29(4)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(4)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(4):int32 addr=t29(4):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(-43646594:h:NewObj_UsingVtable):int32 addr=t5(-43646594):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(8:sz:cls:a):int32 addr=t2(8):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(19935792:ah:cls:a):ptr:intptr addr=t3(19935792):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s11(EFLGS):uint32 addr=s11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(-165:m:a.work):int32 addr=t13(-165):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(-43645129:h:EnableThreadSuspension):int32 addr=t26(-43645129):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t31(0):int32 addr=t31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t32(ESI):uint32 addr=t32(ESI):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} t33(EBP):uint32 addr=t33(EBP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t34(EBX):uint32 addr=t34(EBX):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} o35(31):int8 addr=o35(31):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm o36(-32):int8 addr=o36(-32):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm o37(-39):int8 addr=o37(-39):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm ======================================================================== __IR_DUMP_END__: stageId=49 stageName=emitter subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=49 stageName=emitter subKind=after.liveness Printing IR emitter - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after emitter ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Block code address: 03C80090 Live at entry: t28(1) t32(28) t33(29) t34(30) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Block code address: 03C80093 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Block code address: 03C800A4 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Block code address: 03C800B4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Block code address: 03C800BC Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Block code address: 03C800C5 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Block code address: 03C800D4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Block code address: 03C800D9 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Block code address: 03C800DB Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=49 stageName=emitter subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=49 stageName=emitter subKind=after Printing IR emitter - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after emitter ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Block code address: 03C80090 03C80090 I0: (AD:t30[t28(ESP)+t29(4)]:cls:java/lang/String[]) =EntryPointPseudoInst 03C80090 I33: PUSH t34(EBX):uint32 03C80091 I32: PUSH t33(EBP):uint32 03C80092 I31: PUSH t32(ESI):uint32 BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Block code address: 03C80093 03C80093 I29: PUSH t3(19935792:ah:cls:a):ptr:intptr 03C80098 I28: PUSH t2(8:sz:cls:a):int32 03C8009D I1: (AD:t27(EAX):cls:a) =CALL t5(-43646594:h:NewObj_UsingVtable):int32 (AU:t2(8:sz:cls:a):int32,t3(19935792:ah:cls:a):ptr:intptr) 03C800A2 I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Block code address: 03C800A4 03C800A4 I2: MethodEntryPseudoInst[a.]--- 03C800A4 I3: MethodEntryPseudoInst[java/lang/Object.]--- 03C800A4 I4: MethodEndPseudoInst[java/lang/Object.]+++ 03C800A4 I5: MethodEndPseudoInst[a.]+++ 03C800A4 I26: (ID:s11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 03C800A6 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 03C800AE I14: (ID:s11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Block code address: 03C800B4 03C800B4 I8: (ID:s11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 03C800BA I9: JNL BB_7_epilog o35(31):int8 (IU:s11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Block code address: 03C800BC 03C800BC I24: PUSH t4(ESI):cls:a D195CE89 I37: NOP 03C800C0 I10: (AD:t14(EAX):cls:man) =CALL t13(-165:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Block code address: 03C800C5 03C800C5 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) 03C800C5 I11: (ID:s11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 03C800CB I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) 03C800CB I15: (ID:s11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 03C800D2 I16: JZ BB_3 o36(-32):int8 (IU:s11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Block code address: 03C800D4 03C800D4 I17: CALL t26(-43645129:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Block code address: 03C800D9 03C800D9 I30: JMP o37(-39):int8 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Block code address: 03C800DB 03C800DB I34: POP t32(ESI):uint32 03C800DC I35: POP t33(EBP):uint32 03C800DD I36: POP t34(EBX):uint32 03C800DE I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=49 stageName=emitter subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=49 stageGroup=IA32 stageName=emitter stageTag=emitter ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=50 stageGroup=IA32 stageName=si_insts stageTag=si_insts ======================================================================== ======================================================================== __STAGE_END__: stageId=50 stageGroup=IA32 stageName=si_insts stageTag=si_insts ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=51 stageGroup=IA32 stageName=gcmap stageTag=gcmap ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=51 stageName=gcmap subKind=after.opnds Printing IR gcmap - after.opnds ======================================================================== .................................................................... a.main: Operands in IA32 LIR CFG after gcmap .................................................................... t30[t28(ESP)+t29(4)]:cls:java/lang/String[] addr=t30[t28(ESP)+t29(4)]:cls:java/lang/String[] Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t28(ESP):uint32 addr=t28(ESP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESP} t29(4):int32 addr=t29(4):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t27(EAX):cls:a addr=t27(EAX):cls:a Initial constraint: Sz32:Mem|GPReg{EAX} Calculated constraint: Sz32:Mem|GPReg{EAX} Location constraint: Sz32:GPReg{EAX} t5(-43646594:h:NewObj_UsingVtable):int32 addr=t5(-43646594):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t2(8:sz:cls:a):int32 addr=t2(8):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t3(19935792:ah:cls:a):ptr:intptr addr=t3(19935792):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t4(ESI):cls:a addr=t4(ESI):cls:a Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} v0(EBX):int32 addr=v0(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t8(0):int32 addr=t8(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s18(EBP):ptr:intptr addr=s18(EBP):ptr:intptr Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t20(FS:[t19(20)]):ptr:int8 addr=t20(FS:[t19(20)]):ptr:int8 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t19(20):int32 addr=t19(20):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s11(EFLGS):uint32 addr=s11(EFLGS):uint32 Initial constraint: Sz32:StatusReg{EFLGS} Calculated constraint: Sz32:StatusReg{EFLGS} Location constraint: Sz32:StatusReg{EFLGS} t21(4):ptr:intptr addr=t21(4):ptr:intptr Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t10(20000):int32 addr=t10(20000):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t12(0):int32 addr=t12(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t14(EAX):cls:man addr=t14(EAX):cls:man Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EAX} t13(-165:m:a.work):int32 addr=t13(-165):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm s16(EBX):int32 addr=s16(EBX):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t15(1):int32 addr=t15(1):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t23[s18(EBP)+t22(0)]:int32 addr=t23[s18(EBP)+t22(0)]:int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Mem t22(0):int32 addr=t22(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t24(0):int32 addr=t24(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t25(0):int32 addr=t25(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t26(-43645129:h:EnableThreadSuspension):int32 addr=t26(-43645129):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t17(4):int16 addr=t17(4):int16 Initial constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Calculated constraint: Sz16:Imm|Mem|GPReg{AX|CX|DX|BX|SP|BP|SI|DI} Location constraint: Sz16:Imm t31(0):int32 addr=t31(0):int32 Initial constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:Imm|Mem|GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:Imm t32(ESI):uint32 addr=t32(ESI):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{ESI} t33(EBP):uint32 addr=t33(EBP):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBP} t34(EBX):uint32 addr=t34(EBX):uint32 Initial constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Calculated constraint: Sz32:GPReg{EAX|ECX|EDX|EBX|ESP|EBP|ESI|EDI} Location constraint: Sz32:GPReg{EBX} t35(31):int8 addr=t35(31):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm t36(-32):int8 addr=t36(-32):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm t37(-39):int8 addr=t37(-39):int8 Initial constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Calculated constraint: Sz8:Imm|Mem|GPReg{AL|CL|DL|BL|AH|CH|DH|BH} Location constraint: Sz8:Imm ======================================================================== __IR_DUMP_END__: stageId=51 stageName=gcmap subKind=after.opnds ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=51 stageName=gcmap subKind=after.liveness Printing IR gcmap - after.liveness ======================================================================== ==================================================================== a.main IA32 LIR CFG after gcmap ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Block code address: 03C80090 Live at entry: t28(1) t32(28) t33(29) t34(30) Live at exit: BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Block code address: 03C80093 Live at entry: Live at exit: t4(7) BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Block code address: 03C800A4 Live at entry: t4(7) Live at exit: t4(7) v0(8) s18(10) BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Block code address: 03C800B4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Block code address: 03C800BC Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Block code address: 03C800C5 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Block code address: 03C800D4 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Block code address: 03C800D9 Live at entry: t4(7) v0(8) s18(10) Live at exit: t4(7) v0(8) s18(10) UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] Live at entry: Live at exit: BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Block code address: 03C800DB Live at entry: Live at exit: EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: Live at entry: Live at exit: ======================================================================== __IR_DUMP_END__: stageId=51 stageName=gcmap subKind=after.liveness ======================================================================== ------------------------------------------------------------- ======================================================================== __IR_DUMP_BEGIN__: stageId=51 stageName=gcmap subKind=after Printing IR gcmap - after ======================================================================== ==================================================================== a.main IA32 LIR CFG after gcmap ==================================================================== BB_0_prolog PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: Successors: BB_1 [Prob=1] Layout Succ: BB_1 Block code address: 03C80090 03C80090 I0: (AD:t30[t28(ESP)+t29(4)]:cls:java/lang/String[]) =EntryPointPseudoInst 03C80090 I33: PUSH t34(EBX):uint32 03C80091 I32: PUSH t33(EBP):uint32 03C80092 I31: PUSH t32(ESI):uint32 BB_1 PersistentId = 0 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_0_prolog Successors: BB_2 [Prob=1] UN_5 [Prob=1e-007] Layout Succ: BB_2 Block code address: 03C80093 03C80093 I29: PUSH t3(19935792:ah:cls:a):ptr:intptr 03C80098 I28: PUSH t2(8:sz:cls:a):int32 03C8009D I1: (AD:t27(EAX):cls:a) =CALL t5(-43646594:h:NewObj_UsingVtable):int32 (AU:t2(8:sz:cls:a):int32,t3(19935792:ah:cls:a):ptr:intptr) 03C800A2 I27: MOV t4(ESI):cls:a,t27(EAX):cls:a BB_2 PersistentId = 8 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_1 Successors: BB_3 [Prob=1] Layout Succ: BB_3 Block code address: 03C800A4 03C800A4 I2: MethodEntryPseudoInst[a.]--- 03C800A4 I3: MethodEntryPseudoInst[java/lang/Object.]--- 03C800A4 I4: MethodEndPseudoInst[java/lang/Object.]+++ 03C800A4 I5: MethodEndPseudoInst[a.]+++ 03C800A4 I26: (ID:s11(EFLGS):uint32) =XOR v0(EBX):int32,v0(EBX):int32 03C800A6 I25: MOV s18(EBP):ptr:intptr,t20(FS:[t19(20)]):ptr:int8 03C800AE I14: (ID:s11(EFLGS):uint32) =ADD s18(EBP):ptr:intptr,t21(4):ptr:intptr BB_3 PersistentId = 1 ExecCnt = 99999.9 Loop: Depth=1, hdr, hdr= NULL Predcessors: BB_6 BB_2 BB_15 Successors: BB_7_epilog [Prob=0.1](loopexit)(Br=I9) BB_4 [Prob=0.9](Br=I9) Layout Succ: BB_4 Block code address: 03C800B4 03C800B4 I8: (ID:s11(EFLGS):uint32) =CMP v0(EBX):int32,t10(20000):int32 03C800BA I9: JNL BB_7_epilog t35(31):int8 (IU:s11(EFLGS):uint32) BB_4 PersistentId = 2 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_3 Successors: BB_6 [Prob=1] UN_5 [Prob=1e-007](loopexit) Layout Succ: BB_6 Block code address: 03C800BC 03C800BC I24: PUSH t4(ESI):cls:a D195CE89 I37: NOP 03C800C0 I10: (AD:t14(EAX):cls:man) =CALL t13(-165:m:a.work):int32 (AU:t4(ESI):cls:a) BB_6 PersistentId = 10 ExecCnt = 89999.9 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_4 Successors: BB_14 [Prob=1e-007](Br=I16) BB_3 [Prob=1](backedge)(Br=I16) Layout Succ: BB_14 Block code address: 03C800C5 03C800C5 I18: (AD:s16(EBX):int32) =CopyPseudoInst/MOV (AU:v0(EBX):int32) 03C800C5 I11: (ID:s11(EFLGS):uint32) =ADD s16(EBX):int32,t15(1):int32 03C800CB I12: (AD:v0(EBX):int32) =CopyPseudoInst/MOV (AU:s16(EBX):int32) 03C800CB I15: (ID:s11(EFLGS):uint32) =CMP t23[s18(EBP)+t22(0)]:int32,t24(0):int32 03C800D2 I16: JZ BB_3 t36(-32):int8 (IU:s11(EFLGS):uint32) BB_14 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_6 Successors: UN_5 [Prob=1e-007](loopexit) BB_15 [Prob=1] Layout Succ: BB_15 Block code address: 03C800D4 03C800D4 I17: CALL t26(-43645129:h:EnableThreadSuspension):int32 BB_15 PersistentId = 0 ExecCnt = 0.00899999 Loop: Depth=1, !hdr, hdr=BB_3 Predcessors: BB_14 Successors: BB_3 [Prob=1](backedge) Layout Succ: BB_7_epilog Block code address: 03C800D9 03C800D9 I30: JMP t37(-39):int8 UN_5 PersistentId = 6 ExecCnt = 0.00999999 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_14 BB_1 BB_4 Successors: EN_9 [Prob=1] BB_7_epilog PersistentId = 3 ExecCnt = 9999.99 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_3 Successors: EN_9 [Prob=1] Layout Succ: NULL Block code address: 03C800DB 03C800DB I34: POP t32(ESI):uint32 03C800DC I35: POP t33(EBP):uint32 03C800DD I36: POP t34(EBX):uint32 03C800DE I13: RET t17(4):int16 EN_9 PersistentId = 7 ExecCnt = 10000 Loop: Depth=0, !hdr, hdr=NULL Predcessors: BB_7_epilog UN_5 Successors: ======================================================================== __IR_DUMP_END__: stageId=51 stageName=gcmap subKind=after ======================================================================== ======================================================================== __STAGE_END__: stageId=51 stageGroup=IA32 stageName=gcmap stageTag=gcmap ======================================================================== ======================================================================== __STAGE_BEGIN__: stageId=52 stageGroup=IA32 stageName=info stageTag=info ======================================================================== ======================================================================== __STAGE_END__: stageId=52 stageGroup=IA32 stageName=info stageTag=info ========================================================================