Index: trunk/vm/port/include/port_vmem.h
===================================================================
--- trunk/vm/port/include/port_vmem.h (revision 535850)
+++ trunk/vm/port/include/port_vmem.h (working copy)
@@ -1,10 +1,10 @@
-/*
+/**
* Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
+ * contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
- * the License. You may obtain a copy of the License at
+ * the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
@@ -14,18 +14,15 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-/**
- * @author Alexey V. Varlamov
- * @version $Revision: 1.1.2.1.4.3 $
- */
+/** @version $Revision: 1.1.2.1.4.3 $*/
#ifndef _PORT_VMEM_H_
#define _PORT_VMEM_H_
/**
* @file
- * Virtual memory support
+ * Virtual memory support.
*
- * Functions to manipulate memory pages in virtual address space:
+ * Functions to manipulate memory pages in virtual address space:
* reserve, de/commit, free, control size and access protection of pages.
*/
@@ -57,7 +54,8 @@
/**
* @defgroup vmem_size Memory page size directives
- * These defines can be used instead of explicit calls to port_vmem_page_sizes().
+ * These defines can be used instead of explicit calls to
+ * port_vmem_page_sizes().
* @{
*/
/** System default page size*/
@@ -74,7 +72,8 @@
/**
* Reserves a continuous memory region in the virtual address space
- * of the calling process.
+ * of the calling process.
+ *
* @param[out] block - descriptor for the reserved memory, required for
* further operations with the memory
* @param[in,out] address - desired starting address of the region to allocate. If
@@ -86,10 +85,11 @@
* @param protectionMode - the bit mask of PORT_VMEM_MODE_* flags
* @param pageSize - the desired size of the memory page; should contain
* PORT_VMEM_PAGESIZE_DEFAULT,
- * PORT_VMEM_PAGESIZE_LARGE or the actual size in bytes
+ * PORT_VMEM_PAGESIZE_LARGE or the actual size
+ * in bytes
* @param pool - the auxiliary pool to allocate the descriptor data, etc
* @return APR_SUCCESS if OK; otherwise, an error code.
- * @see port_vmem_page_sizes()
+ * @sa port_vmem_page_sizes()
*/
APR_DECLARE(apr_status_t) port_vmem_reserve(port_vmem_t **block, void **address,
size_t amount,
@@ -97,42 +97,45 @@
size_t pageSize, apr_pool_t *pool);
/**
-* Commits (a part of) the previously reserved memory region. The allocated memory
-* is initialized to zero.
-* @param[in,out] address - the starting address of the region to commit; the returned value
-* may differ due to page alignment
-* @param amount - the size of the region in bytes
-* @param block - the descriptor to the reserved virtual memory
-* @return APR_SUCCESS if OK; otherwise, an error code.
-*/
+ * Commits (a part of) the previously reserved memory region. The allocated
+ * memory is initialized to zero.
+ *
+ * @param[in,out] address - the starting address of the region to commit; the
+ * returned value may differ due to page alignment
+ * @param amount - the size of the region in bytes
+ * @param block - the descriptor to the reserved virtual memory
+ * @return APR_SUCCESS if OK; otherwise, an error code.
+ */
APR_DECLARE(apr_status_t) port_vmem_commit(void **address, size_t amount,
port_vmem_t *block);
/**
-* Decommits the specified region of committed memory. It is safe to
-* decommit a reserved (but not committed) region.
-* @param address - the starting address of the region to decommit
-* @param amount - the size of the region in bytes
-* @param block - the memory region descriptor
-* @return APR_SUCCESS if OK; otherwise, an error code.
-*/
+ * Decommits the specified region of committed memory. It is safe to
+ * decommit a reserved (but not committed) region.
+ *
+ * @param address - the starting address of the region to decommit
+ * @param amount - the size of the region in bytes
+ * @param block - the memory region descriptor
+ * @return APR_SUCCESS if OK; otherwise, an error code.
+ */
APR_DECLARE(apr_status_t) port_vmem_decommit(void *address, size_t amount,
port_vmem_t *block);
/**
-* Releases previously reserved virtual memory region as a whole.
-* If the region was committed, the function first decommits it.
-* @param block - the memory region descriptor
-* @return APR_SUCCESS if OK; otherwise, an error code.
-*/
+ * Releases previously reserved virtual memory region as a whole.
+ * If the region was committed, the function first decommits it.
+ *
+ * @param block - the memory region descriptor
+ * @return APR_SUCCESS if OK; otherwise, an error code.
+ */
APR_DECLARE(apr_status_t) port_vmem_release(port_vmem_t *block);
/**
-* Returns a zero-terminated array of supported memory page sizes.
-* The first element refers to the system default size and is guaranteed
-* to be non-zero. Subsequent elements (if any) provide large page
-* sizes.
-*/
+ * Returns a zero-terminated array of supported memory page sizes.
+ * The first element refers to the system default size and is guaranteed
+ * to be non-zero. Subsequent elements (if any) provide large page
+ * sizes.
+ */
APR_DECLARE(size_t *) port_vmem_page_sizes();
/**
@@ -142,20 +145,20 @@
APR_DECLARE(size_t) port_vmem_used_size();
/**
- * Returns the amount of committed memory in bytes
+ * Returns the amount of committed memory in bytes,
* or 0 if this value could not be calculated.
*/
APR_DECLARE(size_t) port_vmem_committed_size();
/**
- * Returns the amount of reserved memory in bytes
+ * Returns the amount of reserved memory in bytes,
* or 0 if this value could not be calculated.
*/
APR_DECLARE(size_t) port_vmem_reserved_size();
/**
- * Returns the maximum amount of memory which could be reserved in bytes
- * or 0 if this value could not be calculated
+ * Returns the maximum amount of memory, which could be reserved in bytes,
+ * or 0 if this value could not be calculated.
*/
APR_DECLARE(size_t) port_vmem_max_size();
Index: trunk/vm/port/src/encoder/ia32_em64t/enc_defs.h
===================================================================
--- trunk/vm/port/src/encoder/ia32_em64t/enc_defs.h (revision 535850)
+++ trunk/vm/port/src/encoder/ia32_em64t/enc_defs.h (working copy)
@@ -1,10 +1,10 @@
-/*
+/**
* Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
+ * contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
- * the License. You may obtain a copy of the License at
+ * the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
@@ -14,10 +14,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-/**
- * @author Alexander V. Astapchuk
- * @version $Revision: 1.1.2.2.4.4 $
- */
+/** @version $Revision: 1.1.2.2.4.4 $*/
#ifndef _ENCODER_DEFS_H_
#define _ENCODER_DEFS_H_
@@ -35,24 +32,16 @@
#include
#ifndef COUNTOF
- /**
- * Number of items in an array.
- */
+/** Number of items in an array.*/
#define COUNTOF(a) (sizeof(a)/sizeof(a[0]))
#endif
#ifdef _EM64T_
- /**
- * A stack pointer of default platform's size.
- */
+/** A stack pointer of default platform's size.*/
#define REG_STACK RegName_RSP
- /**
- * A max GP register (with a highest index number)
- */
+/** A max GP register (with a highest index number)*/
#define REG_MAX RegName_R15
- /**
- * Total number of GP registers including stack pointer.
- */
+/** Total number of GP registers including stack pointer.*/
#define MAX_REGS 15
#else
#define REG_STACK RegName_ESP
@@ -69,35 +58,31 @@
* Luckily, the long type serves as desired.
*/
typedef long int_ptr;
-/**
- * A number of bytes 'eaten' by an ordinary PUSH/POP.
- */
+/** A number of bytes 'eaten' by an ordinary PUSH/POP.*/
#define STACK_SLOT_SIZE (sizeof(void*))
-
-/**
- * A recommended by Intel Arch Manual aligment for instructions that
- * are targets for jmps.
+/** A recommended by Intel Arch Manual aligment for instructions that are targets
+ * for jmps.
*/
#define JMP_TARGET_ALIGMENT (16)
-/**
- * A maximum possible size of native instruction.
- */
+/** A maximum possible size of native instruction.*/
#define MAX_NATIVE_INST_SIZE (15)
-/**
+/**
* The enum OpndKind describes an operand's location - memory, immediate or a register.
* It can be used as a bit mask.
*/
enum OpndKind {
- /**
- * A change must be balanced with at least the following places:
- * Ia32::Constraint-s use the OpndKind as a mask
- * encoder.cpp & encoder_master_info.cpp uses OpndKind as an index for hashing
- * - perhaps there are much more places
- *
- * NOTE: an MMXReg kind is incompatible with the current constraints framework,
- * as it's not encoded as a mask.
- */
+/**
+ * A change must be balanced with at least the following places:
+ *
+ * - Ia32::Constraint-s use the OpndKind as a mask
+ * - encoder.cpp & encoder_master_info.cpp uses OpndKind as an index for hashing
+ * - perhaps there are much more places
+ *
+ *
+ * @note An MMXReg kind is incompatible with the current constraints framework,
+ * as it's not encoded as a mask.
+ */
OpndKind_Null=0,
OpndKind_GPReg = 0x01, OpndKind_MinRegKind = OpndKind_GPReg,
OpndKind_SReg = 0x02,
@@ -127,13 +112,14 @@
enum OpndSize {
- /**
- * A change must be balanced with at least the following places:
- * Ia32IRConstants.h :: getByteSize() uses some presumptions about OpndSize_ values
- * Ia32::Constraint-s use the OpndSize as a mask
- * encoder.cpp & encoder_master_info.cpp uses OpndSize as an index for hashing
- * - perhaps there are much more places
- */
+/**
+ * A change must be balanced with at least the following places:
+ *
+ * - Ia32IRConstants.h :: getByteSize() uses some presumptions about OpndSize_ values
+ * - Ia32::Constraint-s use the OpndSize as a mask
+ * - encoder.cpp & encoder_master_info.cpp uses OpndSize as an index for hashing
+ * - perhaps there are much more places
+ */
OpndSize_Null = 0,
OpndSize_8 = 0x01,
OpndSize_16 = 0x02,
@@ -148,7 +134,7 @@
OpndSize_Default = OpndSize_Any
};
-/**
+/**
* enum OpndRole defines the role of an operand in an instruction
* Can be used as mask to combine def and use. The complete def+use
* info can be combined in 2 bits which is used, say in Encoder::OpndRole.
@@ -170,13 +156,13 @@
RegName_Null = 0,
#ifdef _EM64T_
- /*
- An index part of the RegName-s for RAX-RDI, EAX-ESI, AX-SI and AL-BH is
- the same as the index used during instructions encoding. The same rule
- applies for XMM regsters for IA32.
- For new EM64T registers (both GP and XMM) the index need to be corrected to
- obtain the index used in processor's instructions.
- */
+/**
+ * An index part of the RegName-s for RAX-RDI, EAX-ESI, AX-SI and AL-BH is
+ * the same as the index used during instructions encoding. The same rule
+ * applies for XMM regsters for IA32.
+ * For new EM64T registers (both GP and XMM) the index need to be corrected to
+ * obtain the index used in processor's instructions.
+ */
RegName_RAX = REGNAME(OpndKind_GPReg,OpndSize_64,0),
RegName_RCX = REGNAME(OpndKind_GPReg,OpndSize_64,1),
RegName_RDX = REGNAME(OpndKind_GPReg,OpndSize_64,2),
@@ -402,18 +388,18 @@
enum Mnemonic {
Mnemonic_NULL=0, Mnemonic_Null=Mnemonic_NULL,
-Mnemonic_ADC, // Add with Carry
-Mnemonic_ADD, // Add
-Mnemonic_ADDSD, // Add Scalar Double-Precision Floating-Point Values
-Mnemonic_ADDSS, // Add Scalar Single-Precision Floating-Point Values
-Mnemonic_AND, // Logical AND
+Mnemonic_ADC, /** Add with Carry*/
+Mnemonic_ADD, /** Add*/
+Mnemonic_ADDSD, /** Add Scalar Double-Precision Floating-Point Values*/
+Mnemonic_ADDSS, /** Add Scalar Single-Precision Floating-Point Values*/
+Mnemonic_AND, /** Logical AND*/
-Mnemonic_BSF, // Bit scan forward
-Mnemonic_BSR, // Bit scan reverse
+Mnemonic_BSF, /** Bit scan forward*/
+Mnemonic_BSR, /** Bit scan reverse*/
-Mnemonic_CALL, // Call Procedure
-Mnemonic_CWD, Mnemonic_CDQ=Mnemonic_CWD,// Convert Word to Doubleword/Convert Doubleword to Qua T dword
-Mnemonic_CMOVcc, // Conditional Move
+Mnemonic_CALL, /** Call Procedure*/
+Mnemonic_CWD, Mnemonic_CDQ=Mnemonic_CWD,/** Convert Word to Doubleword/Convert Doubleword to Qua T dword*/
+Mnemonic_CMOVcc, /** Conditional Move*/
CCM(CMOV,O),
CCM(CMOV,NO),
CCM(CMOV,B), CCM(CMOV,NAE), CCM(CMOV,C),
@@ -432,81 +418,69 @@
CCM(CMOV,LE), CCM(CMOV,NG),
CCM(CMOV,NLE), CCM(CMOV,G),
-Mnemonic_CMP, // Compare Two Operands
-Mnemonic_CMPXCHG, // Compare and exchange
+Mnemonic_CMP, /** Compare Two Operands*/
+Mnemonic_CMPXCHG, /** Compare and exchange*/
//
// double -> float
-Mnemonic_CVTSD2SS, // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
+Mnemonic_CVTSD2SS, /** Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value*/
// double -> int32
-Mnemonic_CVTSD2SI, // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
+Mnemonic_CVTSD2SI, /** Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer*/
// double [truncated] -> int32
-Mnemonic_CVTTSD2SI, // Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer
+Mnemonic_CVTTSD2SI, /** Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Doubleword Integer*/
//
// float -> double
-Mnemonic_CVTSS2SD, // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
+Mnemonic_CVTSS2SD, /** Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value*/
// float -> int32
-Mnemonic_CVTSS2SI, // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
+Mnemonic_CVTSS2SI, /** Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer*/
// float [truncated] -> int32
-Mnemonic_CVTTSS2SI, // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
+Mnemonic_CVTTSS2SI, /** Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer*/
//
// int32 -> double
-Mnemonic_CVTSI2SD, // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
+Mnemonic_CVTSI2SD, /** Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value*/
// int32 -> float
-Mnemonic_CVTSI2SS, // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
+Mnemonic_CVTSI2SS, /** Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value*/
-//Mnemonic_CMPXCHG, // Compare and Exchange
-//Mnemonic_CMPXCHG8B, // Compare and Exchange 8 Bytes
-Mnemonic_COMISD, // Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
-Mnemonic_COMISS, // Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
-Mnemonic_DEC, // Decrement by 1
-//Mnemonic_DIV, // Unsigned Divide
-Mnemonic_DIVSD, // Divide Scalar Double-Precision Floating-Point Values
-Mnemonic_DIVSS, // Divide Scalar Single-Precision Floating-Point Values
+//Mnemonic_CMPXCHG, /** Compare and Exchange*/
+//Mnemonic_CMPXCHG8B, /** Compare and Exchange 8 Bytes*/
+Mnemonic_COMISD, /** Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS*/
+Mnemonic_COMISS, /** Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS*/
+Mnemonic_DEC, /** Decrement by 1*/
+//Mnemonic_DIV, /** Unsigned Divide*/
+Mnemonic_DIVSD, /** Divide Scalar Double-Precision Floating-Point Values*/
+Mnemonic_DIVSS, /** Divide Scalar Single-Precision Floating-Point Values*/
+*/
-
#ifdef _HAVE_MMX_
-Mnemonic_EMMS, // Empty MMX Technology State
+Mnemonic_EMMS, /** Empty MMX Technology State*/
#endif
-Mnemonic_FLDCW, // Load FPU control word
-Mnemonic_FADDP,
-Mnemonic_FLDZ,
-Mnemonic_FADD,
-Mnemonic_FSUBP,
-Mnemonic_FSUB,
-Mnemonic_FMUL,
-Mnemonic_FMULP,
-Mnemonic_FDIVP,
-Mnemonic_FDIV,
-Mnemonic_FUCOMPP,
-Mnemonic_FRNDINT,
-Mnemonic_FNSTCW, // Store FPU control word
-Mnemonic_FSTSW, // Store FPU status word
-Mnemonic_FNSTSW, // Store FPU status word
-//Mnemonic_FDECSTP, // Decrement Stack-Top Pointer
-Mnemonic_FILD, // Load Integer
-Mnemonic_FLD, // Load Floating Point Value
-Mnemonic_FCLEX, // Clear Exceptions
-Mnemonic_FCHS, // Change sign of ST0
-Mnemonic_FNCLEX, // Clear Exceptions
+Mnemonic_FLDCW, /** Load FPU control word*/
+Mnemonic_FNSTCW, /** Store FPU control word*/
+Mnemonic_FSTSW, /** Store FPU status word*/*/
+//Mnemonic_FDECSTP, /** Decrement Stack-Top Pointer
+Mnemonic_FILD, /** Load Integer*/
+Mnemonic_FLD, /** Load Floating Point Value*/
+Mnemonic_FCLEX, /** Clear Exceptions*/
+Mnemonic_FCHS, /** Change sign of ST0*/
+Mnemonic_FNCLEX, /** Clear Exceptions*/
-//Mnemonic_FINCSTP, // Increment Stack-Top Pointer
-Mnemonic_FIST, // Store Integer
-Mnemonic_FISTP, // Store Integer, pop FPU stack
-Mnemonic_FISTTP, // Store Integer with Truncation
-Mnemonic_FPREM, // Partial Remainder
-Mnemonic_FPREM1, // Partial Remainder
-Mnemonic_FST, // Store Floating Point Value
-Mnemonic_FSTP, // Store Floating Point Value and pop the FP stack
+//Mnemonic_FINCSTP, /** Increment Stack-Top Pointer*/
+Mnemonic_FIST, /** Store Integer*/
+Mnemonic_FISTP, /** Store Integer, pop FPU stack*/
+Mnemonic_FISTTP, /** Store Integer with Truncation*/
+Mnemonic_FPREM, /** Partial Remainder*/
+Mnemonic_FPREM1, /** Partial Remainder*/
+Mnemonic_FST, /** Store Floating Point Value*/
+Mnemonic_FSTP, /** Store Floating Point Value and pop the FP stack*/
Mnemonic_XCHG,
-Mnemonic_DIV, // Unsigned Divide
-Mnemonic_IDIV, // Signed Divide
-Mnemonic_MUL, // Unsigned Multiply
-Mnemonic_IMUL, // Signed Multiply
-Mnemonic_INC, // Increment by 1
-Mnemonic_INT3, // Call break point
-Mnemonic_Jcc, // Jump if Condition Is Met
+Mnemonic_DIV, /** Unsigned Divide*/
+Mnemonic_IDIV, /** Signed Divide*/
+Mnemonic_MUL, /** Unsigned Multiply*/
+Mnemonic_IMUL, /** Signed Multiply*/
+Mnemonic_INC, /** Increment by 1*/
+Mnemonic_INT3, /** Call break point*/
+Mnemonic_Jcc, /** Jump if Condition Is Met*/
CCM(J,O),
CCM(J,NO),
CCM(J,B), CCM(J,NAE), CCM(J,C),
@@ -523,46 +497,46 @@
CCM(J,NL), CCM(J,GE),
CCM(J,LE), CCM(J,NG),
CCM(J,NLE), CCM(J,G),
-Mnemonic_JMP, // Jump
-Mnemonic_LEA, // Load Effective Address
-Mnemonic_LOOP, // Loop according to ECX counter
-Mnemonic_LOOPE, // Loop according to ECX counter
-Mnemonic_LOOPNE, Mnemonic_LOOPNZ = Mnemonic_LOOPNE, // Loop according to ECX
-Mnemonic_LAHF, // Load Flags into AH
-Mnemonic_MOV, // Move
-Mnemonic_MOVD, // Move Double word
-Mnemonic_MOVQ, // Move Quadword
-/*Mnemonic_MOVS, // Move Data from String to String*/
+Mnemonic_JMP, /** Jump*/
+Mnemonic_LEA, /** Load Effective Address*/
+Mnemonic_LOOP, /** Loop according to ECX counter*/
+Mnemonic_LOOPE, /** Loop according to ECX counter*/
+Mnemonic_LOOPNE, Mnemonic_LOOPNZ = Mnemonic_LOOPNE, /** Loop according to ECX */
+Mnemonic_LAHF, /** Load Flags into AH*/
+Mnemonic_MOV, /** Move*/
+Mnemonic_MOVD, /** Move Double word*/
+Mnemonic_MOVQ, /** Move Quadword*/
+Mnemonic_MOVS, /** Move Data from String to String*/
// MOVS is a special case: see encodign table for more details,
Mnemonic_MOVS8, Mnemonic_MOVS16, Mnemonic_MOVS32,
//
-Mnemonic_MOVSD, // Move Scalar Double-Precision Floating-Point Value
-Mnemonic_MOVSS, // Move Scalar Single-Precision Floating-Point Values
-Mnemonic_MOVSX, // Move with Sign-Extension
-Mnemonic_MOVZX, // Move with Zero-Extend
-//Mnemonic_MUL, // Unsigned Multiply
-Mnemonic_MULSD, // Multiply Scalar Double-Precision Floating-Point Values
-Mnemonic_MULSS, // Multiply Scalar Single-Precision Floating-Point Values
-Mnemonic_NEG, // Two's Complement Negation
-Mnemonic_NOP, // No Operation
-Mnemonic_NOT, // One's Complement Negation
-Mnemonic_OR, // Logical Inclusive OR
+Mnemonic_MOVSD, /** Move Scalar Double-Precision Floating-Point Value*/
+Mnemonic_MOVSS, /** Move Scalar Single-Precision Floating-Point Values*/
+Mnemonic_MOVSX, /** Move with Sign-Extension*/
+Mnemonic_MOVZX, /** Move with Zero-Extend*/
+Mnemonic_MUL, /** Unsigned Multiply*/
+Mnemonic_MULSD, /** Multiply Scalar Double-Precision Floating-Point Values*/
+Mnemonic_MULSS, /** Multiply Scalar Single-Precision Floating-Point Values*/
+Mnemonic_NEG, /** Two's Complement Negation*/
+Mnemonic_NOP, /** No Operation*/
+Mnemonic_NOT, /** One's Complement Negation*/
+Mnemonic_OR, /** Logical Inclusive OR*/
#ifdef _HAVE_MMX_
- Mnemonic_PADDQ, // Add Packed Quadword Integers
- Mnemonic_PAND, // Logical AND
- Mnemonic_POR, // Bitwise Logical OR
- Mnemonic_PSUBQ, // Subtract Packed Quadword Integers
+ Mnemonic_PADDQ, /** Add Packed Quadword Integers*/
+ Mnemonic_PAND, /** Logical AND*/
+ Mnemonic_POR, /** Bitwise Logical OR*/
+ Mnemonic_PSUBQ, /** Subtract Packed Quadword Integers*/
#endif
-Mnemonic_PXOR, // Logical Exclusive OR
-Mnemonic_POP, // Pop a Value from the Stack
-Mnemonic_POPFD, // Pop a Value of EFLAGS register from the Stack
-Mnemonic_PUSH, // Push Word or Doubleword Onto the Stack
-Mnemonic_PUSHFD, // Push EFLAGS Doubleword Onto the Stack
-Mnemonic_RET, // Return from Procedure
+Mnemonic_PXOR, /** Logical Exclusive OR*/
+Mnemonic_POP, /** Pop a Value from the Stack*/
+Mnemonic_POPFD, /** Pop a Value of EFLAGS register from the Stack*/
+Mnemonic_PUSH, /** Push Word or Doubleword Onto the Stack*/
+Mnemonic_PUSHFD, /** Push EFLAGS Doubleword Onto the Stack*/
+Mnemonic_RET, /** Return from Procedure*/
-Mnemonic_SETcc, // Set Byte on Condition
+Mnemonic_SETcc, /** Set Byte on Condition*/
CCM(SET,O),
CCM(SET,NO),
CCM(SET,B), CCM(SET,NAE), CCM(SET,C),
@@ -580,57 +554,59 @@
CCM(SET,LE), CCM(SET,NG),
CCM(SET,NLE), CCM(SET,G),
-Mnemonic_SAL, Mnemonic_SHL=Mnemonic_SAL,// Shift left
-Mnemonic_SAR, // Unsigned shift right
-Mnemonic_ROR, // Rotate right
-Mnemonic_RCR, // Rotate right through CARRY flag
-Mnemonic_ROL, // Rotate left
-Mnemonic_RCL, // Rotate left through CARRY flag
-Mnemonic_SHR, // Signed shift right
-Mnemonic_SHRD, // Double Precision Shift Right
-Mnemonic_SHLD, // Double Precision Shift Left
+Mnemonic_SAL, Mnemonic_SHL=Mnemonic_SAL,/** Shift left*/
+Mnemonic_SAR, /** Unsigned shift right*/
+Mnemonic_ROR, /** Rotate right*/
+Mnemonic_RCR, /** Rotate right through CARRY flag*/
+Mnemonic_ROL, /** Rotate left*/
+Mnemonic_RCL, /** Rotate left through CARRY flag*/
+Mnemonic_SHR, /** Signed shift right*/
+Mnemonic_SHRD, /** Double Precision Shift Right*/
+Mnemonic_SHLD, /** Double Precision Shift Left*/
-Mnemonic_SBB, // Integer Subtraction with Borrow
-Mnemonic_SUB, // Subtract
-Mnemonic_SUBSD, // Subtract Scalar Double-Precision Floating-Point Values
-Mnemonic_SUBSS, // Subtract Scalar Single-Precision Floating-Point Values
+Mnemonic_SBB, /** Integer Subtraction with Borrow*/
+Mnemonic_SUB, /** Subtract*/
+Mnemonic_SUBSD, /** Subtract Scalar Double-Precision Floating-Point Values*/
+Mnemonic_SUBSS, /** Subtract Scalar Single-Precision Floating-Point Values*/
-Mnemonic_TEST, // Logical Compare
+Mnemonic_TEST, /** Logical Compare*/
-Mnemonic_UCOMISD, // Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
-Mnemonic_UCOMISS, // Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
+Mnemonic_UCOMISD, /** Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS*/
+Mnemonic_UCOMISS, /** Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS*/
-Mnemonic_XOR, // Logical Exclusive OR
-//
-// packed things,
-//
-Mnemonic_XORPD, // Bitwise Logical XOR for Double-Precision Floating-Point Values
-Mnemonic_XORPS, // Bitwise Logical XOR for Single-Precision Floating-Point Values
+Mnemonic_XOR, /** Logical Exclusive OR*/
+/**
+ *@name Packed Things
+ * @{
+ */
+Mnemonic_XORPD, /** Bitwise Logical XOR for Double-Precision Floating-Point Values*/
+Mnemonic_XORPS, /** Bitwise Logical XOR for Single-Precision Floating-Point Values*/
-Mnemonic_CVTDQ2PD, // Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
-Mnemonic_CVTTPD2DQ, // Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
+Mnemonic_CVTDQ2PD, /** Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values*/
+Mnemonic_CVTTPD2DQ, /** Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers*/
-Mnemonic_CVTDQ2PS, // Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
-Mnemonic_CVTTPS2DQ, // Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers
-//
-// String operations
-//
-Mnemonic_STD, // Set direction flag
-Mnemonic_CLD, // Clear direction flag
-Mnemonic_SCAS, // Scan string
-Mnemonic_STOS, // Store string
+Mnemonic_CVTDQ2PS, /** Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values*/
+Mnemonic_CVTTPS2DQ, /** Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers*/
+/** @}*/
+/**
+ * @name String Operations
+ * @{
+ */
+Mnemonic_STD, /** Set direction flag*/
+Mnemonic_CLD, /** Clear direction flag*/
+Mnemonic_SCAS, /** Scan string*/
+Mnemonic_STOS, /** Store string*/
+
//
-Mnemonic_WAIT, // Check pending pending unmasked floating-point exception
+Mnemonic_WAIT, /** Check pending pending unmasked floating-point exception*/
//
Mnemonic_Count
};
-
+/** @}*/
#undef CCM
-/**
- * @brief Instruction prefixes, according to arch manual.
- */
+/** Instruction prefixes, according to arch manual.*/
enum InstPrefix {
InstPrefix_Null = 0,
// Group 1
@@ -670,16 +646,15 @@
}
/**
- * @brief Returns #RegName for a given name.
+ * Returns #RegName for a given name.
*
* Name is case-insensitive.
+ *
* @param regname - string name of a register
* @return #RegName for the given name, or #RegName_Null if name is invalid
*/
RegName getRegName(const char * regname);
-/**
- * Constructs RegName from the given OpndKind, size and index.
- */
+/** Constructs RegName from the given OpndKind, size and index.*/
inline RegName getRegName(OpndKind k, OpndSize s, int idx)
{
return (RegName)REGNAME(k,s,idx);
@@ -692,22 +667,18 @@
return 1<<(reg&0xff);
}
/**
- * @brief Extracts #RegKind from the #RegName.
+ * Extracts #RegKind from the #RegName.
*/
inline OpndKind getRegKind(RegName reg)
{
return (OpndKind)(reg>>24);
}
-/**
- * @brief Extracts #OpndSize from #RegName.
- */
+/** Extracts #OpndSize from #RegName.*/
inline OpndSize getRegSize(RegName reg)
{
return (OpndSize)((reg>>16)&0xFF);
}
-/**
- * Extracts an index from the given RegName.
- */
+/** Extracts an index from the given RegName.*/
inline unsigned char getRegIndex(RegName reg)
{
return (unsigned char)(reg&0xFF);
@@ -756,7 +727,7 @@
}
/**
- * brief Tests two RegName-s of the same kind for equality.
+ * Tests two RegName-s of the same kind for equality.
*
* @note Does work for 8 bit general purpose registers (AH, AL, BH, BL, etc).
*/
Index: trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h
===================================================================
--- trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h (revision 535850)
+++ trunk/vm/port/src/encoder/ia32_em64t/enc_prvt.h (working copy)
@@ -1,10 +1,10 @@
-/*
+/**
* Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
+ * contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The ASF licenses this file to You under the Apache License, Version 2.0
* (the "License"); you may not use this file except in compliance with
- * the License. You may obtain a copy of the License at
+ * the License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
@@ -14,22 +14,19 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-/**
- * @author Alexander V. Astapchuk
- * @version $Revision: 1.1.2.2.4.4 $
- */
+/** @version $Revision: 1.1.2.2.4.4 $*/
#ifndef __ENC_PRVT_H_INCLUDED__
#define __ENC_PRVT_H_INCLUDED__
#include "enc_base.h"
ENCODER_NAMESPACE_START
-/*
+/**
* @file
* @brief Contains some definitions/constants and other stuff used by the
- * Encoder internally.
+ * Encoder internally.
*/
-
+
enum OpcodeByteKind {
//OpcodeByteKind_Opcode = 0x0000,
OpcodeByteKind_ZeroOpcodeByte = 0x0100,
@@ -62,27 +59,23 @@
OpcodeByteKind_REX_W = 0x1300,
#endif
OpcodeByteKind_plus_i = 0x1400,
- /**
- * a special marker, means 'no opcode on the given position'
- * used in opcodes array, to specify the empty slot, say
- * to fill an em64t-specific opcode on ia32.
- * last 'e' made lowercase to avoid a mess with 'F' in
- * OpcodeByteKind_LAST .
- */
+/**
+ * A special marker, means 'no opcode on the given position'
+ * used in opcodes array, to specify the empty slot, say
+ * to fill an em64t-specific opcode on ia32.
+ * last 'e' made lowercase to avoid a mess with 'F' in
+ * OpcodeByteKind_LAST .
+ */
OpcodeByteKind_EMPTY = 0xFFFE,
- /**
- * a special marker, means 'no more opcodes in the array'
- * used in in opcodes array to show that there are no more
- * opcodes in the array for a given mnemonic.
- */
+/**
+ * A special marker, means 'no more opcodes in the array'
+ * used in in opcodes array to show that there are no more
+ * opcodes in the array for a given mnemonic.
+ */
OpcodeByteKind_LAST = 0xFFFF,
- /**
- * a mask to extract the OpcodeByteKind
- */
+/** A mask to extract the OpcodeByteKind*/
OpcodeByteKind_KindMask = 0xFF00,
- /**
- * a mask to extract the opcode byte when presented
- */
+/** A mask to extract the opcode byte when presented*/
OpcodeByteKind_OpcodeMask = 0x00FF
};
@@ -215,9 +208,7 @@
#endif
-/**
- * @brief Represents the REX part of instruction.
- */
+/** @brief Represents the REX part of instruction.*/
struct Rex {
unsigned char b : 1;
unsigned char x : 1;
@@ -227,18 +218,14 @@
unsigned int :24;
};
-/**
- * @brief Describes SIB (scale,index,base) byte.
- */
+/** @brief Describes SIB (scale,index,base) byte.*/
struct SIB {
unsigned char base:3;
unsigned char index:3;
unsigned char scale:2;
unsigned int padding:24;
};
-/**
- * @brief Describes ModRM byte.
- */
+/** @brief Describes ModRM byte.*/
struct ModRM
{
unsigned char rm:3;
@@ -247,12 +234,10 @@
unsigned int padding:24;
};
-
-
/**
-* exactly the same as EncoderBase::OpcodeDesc, but also holds info about
-* platform on which the opcode is applicable.
-*/
+ * Exactly the same as EncoderBase::OpcodeDesc, but also holds info about
+ * platform on which the opcode is applicable.
+ */
struct OpcodeInfo {
enum platform { all, em64t, ia32 };
platform platf;
@@ -263,30 +248,20 @@
/**
* @defgroup MF_ Mnemonic flags
-*/
+ */
- /**
- * Operation has no special properties.
- */
+/** Operation has no special properties.*/
#define MF_NONE (0x00000000)
- /**
- * Operation affects flags
- */
+/** Operation affects flags*/
#define MF_AFFECTS_FLAGS (0x00000001)
- /**
- * Operation uses flags - conditional operations, ADC/SBB/ETC
- */
+/** Operation uses flags - conditional operations, ADC/SBB/ETC*/
#define MF_USES_FLAGS (0x00000002)
- /**
- * Operation is conditional - MOVcc/SETcc/Jcc/ETC
- */
+/** Operation is conditional - MOVcc/SETcc/Jcc/ETC*/
#define MF_CONDITIONAL (0x00000004)
-/**
- * Operation is symmetric - its args can be swapped (ADD/MUL/etc).
- */
+/** Operation is symmetric - its args can be swapped (ADD/MUL/etc).*/
#define MF_SYMMETRIC (0x00000008)
/**
- * Operation is XOR-like - XOR, SUB - operations of 'arg,arg' is pure def,
+ * Operation is XOR-like - XOR, SUB - operations of 'arg,arg' is pure def,
* without use.
*/
#define MF_SAME_ARG_NO_USE (0x00000010)
@@ -294,39 +269,35 @@
///@} // ~MNF
/**
- * @see same structure as EncoderBase::MnemonicDesc, but carries
+ * @sa The same structure as EncoderBase::MnemonicDesc, but carries
* MnemonicInfo::OpcodeInfo[] instead of OpcodeDesc[].
* Only used during prebuilding the encoding tables, thus it's hidden under
* the appropriate define.
*/
struct MnemonicInfo {
- /**
- * The mnemonic itself
- */
+/** The mnemonic itself*/
Mnemonic mn;
- /**
- * Various characteristics of mnemonic.
- * @see MF_
- */
+/**
+ * Various characteristics of mnemonic.
+ * @sa MF_
+ */
unsigned flags;
- /**
- * Number of args/des/uses/roles for the operation. For the operations
- * which may use different number of operands (i.e. IMUL/SHL) use the
- * most common value, or leave '0' if you are sure this info is not
- * required.
- */
+/**
+ * Number of args/des/uses/roles for the operation. For the operations
+ * which may use different number of operands (i.e. IMUL/SHL) use the
+ * most common value, or leave '0' if you are sure this info is not
+ * required.
+ */
EncoderBase::OpndRolesDesc roles;
- /**
- * Print name of the mnemonic
- */
+/** Print name of the mnemonic*/
const char * name;
- /**
- * Array of opcodes.
- * The terminating opcode description always have OpcodeByteKind_LAST
- * at the opcodes[i].opcode[0].
- * The size of '20' has nothing behind it, just counted the max
- * number of opcodes currently used.
- */
+/**
+ * Array of opcodes.
+ * The terminating opcode description always have OpcodeByteKind_LAST
+ * at the opcodes[i].opcode[0].
+ * The size of '20' has nothing behind it, just counted the max
+ * number of opcodes currently used.
+ */
OpcodeInfo opcodes[20];
};