diff --git a/vm/jitrino/src/translator/java/JavaByteCodeTranslator.cpp b/vm/jitrino/src/translator/java/JavaByteCodeTranslator.cpp index d28cc19..82e6d9c 100644 --- a/vm/jitrino/src/translator/java/JavaByteCodeTranslator.cpp +++ b/vm/jitrino/src/translator/java/JavaByteCodeTranslator.cpp @@ -2768,6 +2768,12 @@ JavaByteCodeTranslator::genArrayCopyRepM uint32 numArgs, Opnd ** srcOpnds) { +#ifdef _EM64T_ + // FIXME: this was not tested (and does not work) on EM64T. + if (true) { + return false; + } +#endif if( !methodIsArraycopy(methodDesc) || !arraycopyOptimizable(methodDesc,numArgs,srcOpnds) ) { diff --git a/vm/port/src/encoder/ia32_em64t/enc_prvt.h b/vm/port/src/encoder/ia32_em64t/enc_prvt.h index 065ee7f..f98b992 100644 --- a/vm/port/src/encoder/ia32_em64t/enc_prvt.h +++ b/vm/port/src/encoder/ia32_em64t/enc_prvt.h @@ -145,6 +145,9 @@ enum OpcodeByteKind { #define CL {OpndKind_GPReg, OpndSize_8, RegName_CL} #define ECX {OpndKind_GPReg, OpndSize_32, RegName_ECX} +#ifdef _EM64T_ + #define RCX {OpndKind_GPReg, OpndSize_64, RegName_RCX} +#endif #define DX {OpndKind_GPReg, OpndSize_16, RegName_DX} #define EDX {OpndKind_GPReg, OpndSize_32, RegName_EDX} diff --git a/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp b/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp index 20dd3a0..c6d3857 100644 --- a/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp +++ b/vm/port/src/encoder/ia32_em64t/enc_tabl.cpp @@ -745,7 +745,10 @@ BEGIN_OPCODES() */ // {OpcodeInfo::all, {0xF7, _5}, {EDX, EAX, r_m32}, D_DU_U }, - {OpcodeInfo::em64t, {REX_W, 0xF7, _5}, {RDX, RAX, r_m64}, D_DU_U }, + //todo: this opcode's hash conflicts with IMUL r64,r_m64 - they're both 0. + // this particular is not currently used, so we may safely drop it, but need to + // revisit the hash implementation + // {OpcodeInfo::em64t, {REX_W, 0xF7, _5}, {RDX, RAX, r_m64}, D_DU_U }, // {OpcodeInfo::all, {Size16, 0x0F, 0xAF, _r}, {r16,r_m16}, DU_U }, {OpcodeInfo::all, {0x0F, 0xAF, _r}, {r32,r_m32}, DU_U }, @@ -1316,18 +1319,21 @@ the specific mnemonic - the same is in t BEGIN_MNEMONIC(MOVS8, MF_NONE, DU_DU_DU) BEGIN_OPCODES() {OpcodeInfo::ia32, {0xA4}, {r32,r32,ECX}, DU_DU_DU }, + {OpcodeInfo::em64t, {0xA4}, {r64,r64,RCX}, DU_DU_DU }, END_OPCODES() END_MNEMONIC() BEGIN_MNEMONIC(MOVS16, MF_NONE, DU_DU_DU) BEGIN_OPCODES() {OpcodeInfo::ia32, {Size16, 0xA5}, {r32,r32,ECX}, DU_DU_DU }, + {OpcodeInfo::em64t, {Size16, 0xA5}, {r64,r64,RCX}, DU_DU_DU }, END_OPCODES() END_MNEMONIC() BEGIN_MNEMONIC(MOVS32, MF_NONE, DU_DU_DU) BEGIN_OPCODES() {OpcodeInfo::ia32, {0xA5}, {r32,r32,ECX}, DU_DU_DU }, + {OpcodeInfo::em64t, {0xA5}, {r64,r64,RCX}, DU_DU_DU }, END_OPCODES() END_MNEMONIC()